This invention relates to programmable input offset gain amplifiers, and more particularly to circuitry which provides a substantially improved input offset voltage canceling range and which also provides substantially improved noise performance.
“Prior Art” FIG. 1A shows a conventional amplifier stage 1A which includes P-channel input transistors M1 and M2 having their sources coupled to current source 2, which produces a tail current Itail1. The gates of transistors M1 and M2 are connected to Vin+ and Vin−, respectively. The drain of input transistor M1 is connected by conductor 5A to the (−) input of an output stage 13 and to the drain of a N-channel load transistor M3. The drain of input transistor M2 is connected by conductor 5B to the (+) input of output stage 13 and to the drain of a N-channel load transistor M4. The gates of load transistors M3 and M4 are connected to the gate and drain of a diode-connected N-channel current mirror input transistor M5 by means of conductor 16, which is also connected to a current source 3 producing a current Itail1/2, which is mirrored through load transistors M3 and M4. The upper terminals of current sources 2 and 3 are connected to a supply voltage V+. The sources of transistors M3, M4 and M5 are connected to ground. Output stage 13 accepts and amplifies differential signals on conductors 5A and 5B and feeds them back to transistors M6 and M7 during the auto-zero cycle. The (+) and (−) outputs of output stage 13 are connected to Vout+ and Vout−, respectively.
Referring to Prior Art FIG. 1B, the addition of transistors M6-M7, capacitors C1 and C2, tail current source 7 producing tail current Itail2, four single pole, double throw switches (or switch circuits) 11A, 11B, 14 and 15 to differential amplifier stage 1A of FIG. 1A results in the conventional auto-zero amplifier 1B shown in FIG. 1B. Each of the switches has an “A” terminal to which the pole of the switch is connected during a time interval “A” and a “B” terminal to which the pole is connected during a time interval “B”. A conductor 9 is connected between the “B” terminals of input switches 11A and 11B. Current source 7, which produces tail current Itail2, is connected between V+ and the sources of N-channel transistors M6 and M7, the gates of which are connected by conductors 17A and 17B to the upper terminals of capacitors C1 and C2, respectively, the lower terminals thereof being connected to ground. The drains of transistors M6 and M7 are connected to conductors 5A and 5B, respectively. Conductor 17A is connected to the B terminal of switch 15 and conductor 17B is connected to the B terminal of switch 14. The A terminal of switch 14 is connected to Vout+ and the A terminal of switch 15 is connected to Vout−. The pole terminal of switch 14 is connected by conductor 6A to the (+) output of output stage 13, and the pole terminal of switch 15 is connected by conductor 6B to the (−) output of output stage 13. Conventional external clocking and switch control circuitry (not shown) also are provided to ensure that all of the switches are opened and closed in the appropriate manner and at the appropriate times so as to cancel any input offset voltage of auto-zero amplifier 1B.
A modified auto-zero amplifier stage as shown in Prior Art FIG. 1C is sometimes used as the input stage for a programmable input offset canceling amplifier circuit. For example, the input stage topology of the prior art offset canceling auto-zero amplifier 1C in FIG. 1C consists of an auto-zero stage as shown in FIG. 1B with the further addition of a programmable precision offset reference voltage generator 18 coupled between the B terminals of input switches 11A and 11B. Offset reference voltage regulator 18 produces a programmable input offset reference voltage VOSRef, as in the PGA309 programmable input reference voltage amplifier being marketed by the present assignee. The programmable offset voltage reference VOSRef in FIG. 1C replaces the short circuit conductor 9 connected between input switch terminals “B” in FIG. 1B so that the auto-zero portion of the circuit may be calibrated to a programmable input offset value instead of to “zero”.
While prior art auto-zero amplifier stages are very effective for canceling small offset voltages produced as a result of device mismatches of transistors which are designed to be precisely matched, it should be noted that such auto-zero amplifier stages suffer substantial performance degradation when used to generate large values of the programmed input offset voltage VOSRef. The performance degradation can include noise performance, which is the primary performance degradation. The performance degradation also can include gm (transconductance) variations which cause many other undesirable effects such as gain and slew rate variations, stability issues, stage power requirements etc.
It should be understood that by adding the offset voltage reference component VOSRef and significantly modifying transistor sizes and bias values, the prior art programmable auto-zero circuit 1C of FIG. 1C changes the operation of the auto-zero circuit of FIG. 1B from performing the function of eliminating small amplifier input offset voltages to the very different function of providing potentially large programmable input offset voltage values. While the simple auto-zero stage topology of FIG. 1B is known to excel at zeroing out (i.e. canceling or removing) the small offset voltages and drift created by device mismatches and errors, that topology suffers significant performance degradation when providing large programmed input offset values.
The following explanation of the circuit operation of auto-zero amplifier 1C of FIG. 1C and design trade-offs thereof reveals the causes of the foregoing performance degradation problems. The four switches 11A, 11B, 14 and 15 in FIG. 1C produce two distinctly different circuit topologies during the two alternating modes of operation during the previously mentioned alternating A and B time periods. In operation, the previously mentioned external clocking and driver circuits ensure that all switches change their positions simultaneously as the operating mode changes at the end of alternating A and B time periods. During time period A, all switches are set to the A position, and during time period B all switches are set to the B position. During the A time period, the circuit is a simple differential amplifier with an input offset caused by, among other factors, the charges stored on capacitors C1 and C2. Transistors M1 through M4 form a simple differential input stage that provides a differential current to the output stage of differential amplifier 1C. Any difference in voltage across capacitors C1 and C2 produces an imbalance in the drain currents of transistors M6 and M7 which, when reflected back through input transistors M1 and M2, produces an input offset voltage in programmable offset auto-zero amplifier 1C.
During time period B, the circuit of FIG. 1C does not operate as an amplifier at all, but rather as a calibration system used to capture an offset voltage across C1 and C2 that, when reflected through input transistors M1 and M2, produces an input offset voltage equal and opposite to the programmed reference voltage VOSRef. The output conductors Vout− and Vout+ do not provide an amplified signal during time period B. Instead the output signals on conductors 6B and 6A are fed back to charge capacitors C1 and C2, respectively, producing the differential voltage across transistors M6-M7 as required to null the differential current from input transistors M1 and M2 in response to the programmed offset voltage VOSRef. Therefore, when the next A time period arrives, the circuit functions as a differential amplifier having an input offset voltage equal to that provided by VOSRef during the previous B time period. This way any desired value of input offset voltage may be produced at the input of amplifier 1C by programming VOSRef during time period B.
As may be seen by comparing FIGS. 1B and 1C, with the exception Of VOSRef, the topology of amplifier 1C is identical to that of a conventional auto-zero amplifier as shown in FIG. 1B. In order to provide a large input offset voltage range, device sizes and bias currents of auto-zero amplifier 1B are chosen which severely limit the performance of amplifier 1C. It should be understood that in the traditional auto-zero amplifier of FIG. 1B, only very small imbalances of current need to be canceled by means of transistors M6 and M7. These small imbalances are caused by mismatches of transistor pairs M1-M2 and M3-M4, which tend to be at most a few percent of Itail1.
Therefore, when designing the circuit of FIG. 1B, one may choose Itail2<<Itail1. In this case the bias current through input transistors M1 and M2 may remain unchanged while the current through transistors M3-M5 increases by only a few percent over the conventional non-auto-zero stage of FIG. 1A. Devices M1-M5 are therefore sized and optimized in the same way when designing the circuits of FIGS. 1A and 1B. This typically means choosing the transistor W(channel width)/L (channel length) ratios (hereinafter referred to as “Z” ratios or “geometry ratios”), the gm's, and the tail currents to minimize noise and power while matching them to the output stage so as to meet various bandwidth, slew-rate and other specifications. When considering input referred noise, gain, and bandwidth, the input transistor pair M1 and M2 transconductance (gm) is especially important. For FETs (field effect transistors), gm is proportional to the square root of the transistor drain current and to its channel-width-to-channel-length ratio Z. To make the gm of the input transistor pair large, one would tend to make the channel widths (W) of input transistors M1 and M2 large, their channel lengths (L) small and the drain current of each (which is ½ Itail1) large within the practical limits associated with these parameters.
It is well known that auto-zero amplifiers effectively eliminate low frequency noise and errors for frequencies significantly lower than the auto-zero switching frequency. It is also known that noise at frequencies above the auto-zero switching frequency may be folded back by auto-zero circuitry and appear as aliased noise to the circuit. Therefore, it is the higher frequency thermal noise that will be considered when noise is discussed herein. The noise analysis proceeds as though amplifier 1C were always in its amplifying mode. It should be noted that if thermal noise of an auto-zero amplifier is reduced (or increased) due to device design constraints of the circuit in a non-switched amplifying mode, then the noise of that circuit will also be reduced (or increased) when operated in a switching auto-zero mode.
As explained earlier, thermal noise performance is degraded in the prior art programmable input offset amplifier 1C of FIG. 1C when it is designed to provide a wide programmable input offset voltage range. This is due to conflicting device requirements when trying to optimize for both noise and for a wide offset voltage range. To understand this conflict, the thermal noise of the circuit devices is considered in the following manner. The square of the average thermal noise current i2=4 kT(⅔gm)Δf generated by a FET (field effect transistor) is proportional to its gm. (See “Analysis and Design of Analog Integrated Circuits”, 3rd edition, Gray/Myer pp. 727). This is modeled as shown in FIG. 2, wherein each transistor in FIG. 1C is represented by an ideal FET (field effect transistor) with a noise generating current source coupled in parallel with its source and drain. The noise characteristics of amplifier 1C may be analyzed by noting that output stage 13 will amplify any differential noise current injected into its input conductors 5A and 5B. Since the circuits of FIGS. 1B and 1C are so similar, their noise analysis is also similar. It may be seen that the noise sources associated with transistors M1, M3 and M6 inject current noise into the inverting terminal (−) of the output stage while the noise sources from transistors M2, M4 and M7 inject into the non-inverting terminal (+). Therefore, all FET noise sources contribute to the overall amplifier noise (except for transistor M5, the noise source of which is mirrored equally by transistors M3 and M4 and therefore appears as common mode noise to the output stage and therefore is canceled. Similarly, noise from the Itail1 and Itail2 current sources is common mode noise when the gm's of transistors M1 and M2 and also M6 and M7 are balanced).
The total effect of the foregoing noise sources shown in Prior Art FIG. 2 may be combined into one equivalent noise voltage source at the input. This is done by transforming the current noise at the drain of input transistors M1 and M2 to noise at the gates of the transistors by dividing it by the gm of the input transistors M1 and M2. For the programmable input offset amplifier 1C as shown in FIG. 2, the total average noise current on the drain of transistor M1
      is    ⁢                  ⁢                  4        ⁢                                  ⁢                  kT          ⁡                      (                                          2                3                            ⁢                              (                                                      g                                          m                      ⁢                                                                                          ⁢                      1                                                        +                                      g                                          m                      ⁢                                                                                          ⁢                      3                                                        +                                      g                                          m                      ⁢                                                                                          ⁢                      6                                                                      )                                      )                          ⁢        Δ        ⁢                                  ⁢        f              ,which transforms to a noise voltage source of value
            4      ⁢                          ⁢              kT        ⁡                  (                                    2              3                        ⁢                          (                                                g                                      m                    ⁢                                                                                  ⁢                    1                                                  +                                  g                                      m                    ⁢                                                                                  ⁢                    3                                                  +                                  g                                      m                    ⁢                                                                                  ⁢                    6                                                              )                                )                    ⁢      Δ      ⁢                          ⁢      f            g          m      ⁢                          ⁢      1      in series with the gate of input transistor M1. Similarly an equivalent noise source at the gate of transistor M2 of
            4      ⁢                          ⁢              kT        ⁡                  (                                    2              3                        ⁢                          (                                                g                                      m                    ⁢                                                                                  ⁢                    2                                                  +                                  g                  m4                                +                                  g                                      m                    ⁢                                                                                  ⁢                    7                                                              )                                )                    ⁢      Δ      ⁢                          ⁢      f            g          m      ⁢                          ⁢      2      may be shown to represent the noise introduced by the noise sources associated with transistors M2, M4 and M7. These noise sources may be combined to provide a single equivalent input-referred average noise source with the value
            4      ⁢                          ⁢      kT      ⁢              2        3            ⁢      Δ      ⁢                          ⁢              f        ⁡                  [                                                                      g                                      m                    ⁢                                                                                  ⁢                    1                                                  +                                  g                                      m                    ⁢                                                                                  ⁢                    3                                                  +                                  g                                      m                    ⁢                                                                                  ⁢                    6                                                                              g                                  m                  ⁢                                                                          ⁢                  1                                2                                      +                                                            g                                      m                    ⁢                                                                                  ⁢                    2                                                  +                                  g                                      m                    ⁢                                                                                  ⁢                    4                                                  +                                  g                                      m                    ⁢                                                                                  ⁢                    7                                                                              g                                  m                  ⁢                                                                          ⁢                  2                                2                                              ]                      .
When designing the conventional auto-zero amplifier 1B of FIG. 1B, the designer may minimize thermal noise by making gm1>>(gm3+gm6) and gm2>>(gm4+gm7). This may be done by increasing the channel-width-to-channel-length (i.e., W/L) geometry ratio Z1 and Z2 of transistors M1 and M2, respectively, and by decreasing the geometry ratios Z3, Z4, Z6, and Z7 and decreasing Itail2. Increasing Itail1 also reduces noise, but it increases gm1, gm2, gm3, and gm4 simultaneously and is therefore not as effective as increasing Z1 and Z2. It is possible to decrease Z3 and Z4 to counter the effect of increased current but requirements on the available drain-to-source voltage VDS of transistors M3 and M4 constrain these parameters.
In the case of the standard auto-zero amplifier of FIG. 1B, where Itail2 may be as low as only a few percent of Itail1, it is relatively easy to ensure that gm6,7<<gm1,2. The addition of transistors M6 and M7 therefore does not detract significantly from the thermal noise performance available in the simple non-auto-zero amplifier of FIG. 1A. Furthermore, since Itail2<<Itail1, the current through transistors M3 and M4 does not change significantly with the addition of Itail2 and therefore their required sizes are not substantially different than they would be in the simple non-auto-zero amplifier of FIG. 1A.
In other words, the addition of the auto-zero circuitry of FIG. 1B to the conventional differential amplifier stage 1A of FIG. 1A does not substantially change gm3 or gm4 or their contribution to thermal noise. The auto-zero stage may perform very nearly the same as a simple amplifier would when optimized for thermal noise. Similar analysis shows that other performance parameters such as bandwidth, gain and slew rate also are strongly affected by the gm of the input transistor and are not substantially changed by the addition of a small auto-zero differential pair when designed to nullify only small mismatch-generated offset voltages.
Therefore, in most respects auto-zero amplifier 1B of FIG. 1B may be easily designed to perform as well as the simple amplifier of FIG. 1A but with the added benefit of very low input offset and drift. However, when the stage 1C of FIG. 1C is required to produce large programmed input offset voltages such as +/−50 to +/−100 millivolts (as would be highly desirable), it is no longer possible to ensure that Itail1>>Itail2. In fact, for the circuit of FIG. 1C to provide such large input offset values, it is required that Itail2 is approximately equal to Itail1, so that the current densities of transistors M1 and M2 may vary widely. It is the difference in overdrives (VGS−VT) of the input transistors M1 and M2 that produces the programmed input offset voltage in the circuits of FIGS. 1C and 2. The overdrives VGS−VT of the input transistors M1 and M2 are a relatively weak function (i.e., the square root) of their drain currents since
            V      gs        -          V      T        =                              I          D                kZ              .  When Itail1 is evenly divided between transistors M1 and M2, both operate with an identical overdrive of
            I              tail        ⁢                                  ⁢        1                    2      ⁢                          ⁢      kZ      and there is no input offset voltage. By unbalancing the currents through transistors M1 and M2, offset voltages up to a maximum of
  ±                    I                  tail          ⁢                                          ⁢          1                    kZ      may be programmed.
As may be seen from the graph in FIG. 3, which shows Normalized Input Offset vs Current in Transistor M1, a current imbalance between input transistors M1 and M2 of 93% to 7% of Itail1 is required to provide an input offset voltage of
            I              tail        ⁢                                  ⁢        1                    2      ⁢                          ⁢      kZ      at the input terminals. Note that the Y axis is normalized to
            I              tail        ⁢                                  ⁢        1                    2      ⁢                          ⁢      kZ      and the Y axis values of +1 and −1 correspond to the X axis % values of 7% and 93% of Itail1 in transistor M1. Even to reach this value, which is 70% of the theoretical maximum available offset, an input device current density difference of more than 13 times is required between transistors M1 and M2. An even larger overdrive is required if substantially more input offset range is desired. A substantially wider input offset range may be obtained either by (1) increasing Itail1 or (2) decreasing the geometry ratio Z of transistors M1 and M2, or both. However, neither option is desirable if minimizing input-referred thermal noise or overall power are important.
Above-mentioned option (1), increasing Itail1, requires a corresponding increase in Itail2, which increases the gm of all of the transistors. The input-referred thermal noise decreases because of the increase of the gm of the input transistors, but this is countered somewhat by the increased noise current from the other transistors and the significantly increased power dissipation of the circuit (the power dissipation increases with the square of the input offset range).
Above-mentioned option (2) for providing substantially more input offset range is to decrease the size of the input transistors (i.e., decrease Z1 and Z2), which increases the overdrive VGS−VT of the input transistors M1 and M2 and therefore increases the programmable offset range. Unfortunately, decreasing the geometry ratio Z of input transistors M1 and M2 also decreases the gm of the pair of input transistors, which significantly increases the input-referred noise of the amplifier stage. The increased power and/or noise described above occurs in programmable offset amplifier 1C as shown in FIGS. 1C and 2 for all programmed offset voltage values (even zero) because of the required changes in transistor geometry ratios Z and bias conditions. The problems become worse when a large input offset voltage is programmed due to the significant decrease of the gm of the input transistor M1 or M2, with its lower current density. (When the current in the input transistors is unbalanced, one of them has increased current and therefore an increased gm and the other input transistor has decreased current and therefore a decreased gm. The net effect is to decrease the gm of the input pair of transistors, wherein the input transistor having the lower gm dominates the gm of the pair.) For example, the case of 93% of Itail1 in transistor M1 and 7% in transistor M2 described above produces an input offset voltage of
                    I                  tail          ⁢                                          ⁢          1                            2        ⁢                                  ⁢        kZ              .The gm of transistor M2 decreases to
            7      50        =      37    ⁢    %  of its nominal value while the gm of transistor M1 increases to
            93      50        =      136    ⁢    %  of its nominal value. The noise currents generated by transistors M2, M7 and M4 change by −39%, +17% and 0%, respectively. The total noise reflected through transistor M2 to the input is more than double the value for the case with no programmed offset. The noise reflected to the input through transistor M1 actually decreases slightly because of its increased gm, but not enough to begin to compensate for the large increase in noise reflected through transistor M2. In addition, since the gm1 and gm2 now differ, noise on Itail1 that was previously canceled by the matched input transistor pair now contributes to the input-referred noise. Another undesirable consequence of programming a large offset is that the effective differential gm of the front end transistor pair M1,M2 is also substantially reduced from its nominal value, which changes all other amplifier specifications that depend on the front end gm, such as gain, bandwidth, etc.
In summary, the problem of prior art programmable offset amplifier 1C of FIG. 1C is that a large imbalance in current density through input transistors M1 and M2 is required to produce a large input offset voltage. This is obtained by changing bias currents and transistor geometry ratios from otherwise optimal values, which results in significantly degraded noise, gain, bandwidth and power performance relative to a comparable non-offset generating amplifier. Furthermore, significant tail current is added to the auto-zero stage which ultimately adds noise and power to the devices that carry it.
Thus, there is an unmet need for a programmable offset-canceling amplifier and method which provide a large input offset voltage range and which also avoid the substantial performance degradation that occurs in the prior art when large values of input offset voltage are provided.
There also is an unmet need for a programmable input-offset-canceling amplifier and method which provide a large input offset voltage range and also avoid substantially degraded noise, gain, bandwidth, and power performance caused by changing bias currents and transistor geometry ratios from otherwise optimal values.
There also is an unmet need for a programmable offset-canceling amplifier and method that operate with substantially lower low-noise switching glitches and substantially lower clock feed-through glitches than the prior art.
There also is an unmet need for a programmable offset-canceling amplifier and method that improve the noise performance over the prior art while providing twice its input offset canceling range.